Tutorials by experts will provide review presentation of relevant topics.
Invited papers will introduce the mainstream topics.
Workshops organised in correlation with the ESREF conference will give the opportunity to exchange the know-how and field returns on specific topics.
The conference will be preceded by a half-day Tutorials on Tuesday, October 6th morning on the following topics:
Advanced CMOS - Application of reliability models in circuit design
by STMicroelectronics, France
Fault Isolation in Semiconductor Product, Process, Physical and Package Failure Analysis: Importance and Overview
by Advanced Micro Devices, Singapore
Failure Analysis plays a major role in all areas of the semiconductor company. During product development and 1st Silicon stage, in wafer processes and fabrication as well as assembly/package development.
Different companies and areas may have different FA flows. However almost all FA steps will need to start with fault isolation. Fault isolation is the step where we narrow down the focus area of a failing component or product to a manageable area that will allow us to:
- Improve success of finding the defect that is causing the failure
- Significant speed up Turn-around time for Analysis.
This tutorial will provide an overview of all the available failure analysis fault isolation methodology and tools, not just for device/product level but also expanding to package/assembly and PFA level isolation. We have found fault isolation critically important and just as challenging during package failure analysis as well as during PFA (Physical Failure Analysis) stage of the FA process step. The aim of the tutorial is to provide sufficient depth to each topic including sharing case studies to further emphasize the key points related to each methodology. The tutorial will also cover future directions/roadmaps for the fault isolation techniques.
GaN-HEMTs parasitic and Reliability
by Triquint Semiconductor
Invited papers will introduce the mainstream topics.
Challenges and opportunities in Performance, Reliability and Variability in sub-45nm CMOS Technologies
by STMicroelectronics, France
The GHz race required by recent electronics applications in different fields like mobiles, home entertainment, networking and gaming imposed the development and the implementation of new and critical material and process architecture in sub-45m advanced CMOS Technologies. Those complex new elements helped a lot the intrinsic CMOS performance but may jeopardize the extrinsic one by degrading both the reliability of the electronics compounds and their variability.
This paper proposes a synthesis of the main trade-off between performance/reliability/variability items required in the process development of advanced CMOS nodes.
A technical focus will be highlighted around High-k/metal gate scheme implementation for sub-45nm CMOS technologies by discuting the interest of HK in term of performance enhancement and gate dielectric evolution to meet reliability criteria. A particular focus will be proposed for NBTI.
Beside transistor reliability, we will emphasis main variability sources for such tansistors by demonstrating the role of the geometry and physics effects explaining systematic and random variations.
Finally, we will illustrate the severe impact of advanced CMOS road-map on interconnexion reliability with a specific analysis around TDDB/electromigration trade-off for tight metal pitches.
HCI and NBTI Induced Degradation and Impacts on Circuits Aging in Gate-all-Around Silicon Nanowire Transistors
by Peking Univ, Beijing, China
The silicon nanowire transistor (SNWT) with gate-all-around (GAA) structure can be considered as one of the potential candidates for ultimate scaling due to its superior gate control capability and improved carrier transportation property. In this paper, hot carrier injection (HCI) and DC/AC negative bias temperature instability (NBTI) behavior of n-type and p-type SNWTs with top-down approach is discussed. Abnormal NBTI fluctuation in short-channel SNWTs is observed, with a new on-line Ig method given to suppress this fluctuation. In addition, non-negligible impacts of electron trapping/detrapping on the NBTI stress/recovery characteristics in SNWTs with metal gates is found and analyzed, which is quite different from traditional planar devices. The NBTI behavior is analytically modeled taking account of the impacts from unique structure nature of GAA SNWTs. The performance degradation of the typical logic and analog circuits induced by NBTI is estimated based on the proposed model, with some guidelines provided for reliability improvement of SNWT-based circuits.
Application of Transient Interferometric Mapping for ESD and latch-up analysis
by Institute of Solid-State Electronics, Vienna University of Technology (Austria)
Due to device operation at high current densities and temperatures and complex 3D behavior, rules for ESD and latch-up (LU) safe device/circuit design are not straightforward when downscaling technologies. Limited confidence in physical models under such extreme conditions necessitates experimental verifications of TCAD predictions for library devices. Transient Interferometric Mapping (TIM) method has become an industry-relevant tool for free carrier and thermal mapping of devices and chips with ns time and µm space resolution. The added value of TIM for verification/calibration of TCAD simulation in comparison with pure electrical calibration is well known. TIM tools of TU Vienna will be presented from a perspective of their application area and comparison with other transient analysis techniques. In particular, single-shot feature of TIM for quantitative 2D mapping of thermal power in semiconductor bulk at ns-scale, allowing imaging during destructive events, is unique. We will review TIM studies of trigger behavior, current filamentation and failure modes in BCD DMOS and ESD protection devices under TLP and system-level-ESD – like pulses. TIM analysis of 90nm CMOS technology devices and circuits will also be reviewed: Examples of substrate current dynamics causing transient LU and on-state spreading phenomenon in SCRs will be presented. Finally, TIM studies of ESD and short-time self-heating phenomena in GaN-based HEMTs and lasers will be briefly discussed.
The combinational usage of the laser SQUID microscope, the laser terahertz emission microscope, and fault simulations in non-electrical-contact fault localization
by Osaka Univ., Japan
Recently, in fault localization field, several non-electrical contact techniques have been proposed. The techniques include laser SQUID microscope (L-SQ) and laser terahertz emission microscope (LTEM). Both techniques have the pros and cons. The L-SQ, for examples, can localize an open line in some case, but it requires closed circuit. The LTEM can localize open line and short line, and not requires closed circuit. The LTEM, however, cannot localize an open line in some case. The fault simulations specially designed for L-SQ or LTEM make it efficient to localize faults. The combinational usage of L-SQ, LTEM and the fault simulations makes it possible to localize faults in many cases.
From Component to System Failure Analysis – the future challenge within work-sharing supply chains
by EMPA Material Science&Technology, Switzerland and RoodMicrotec, Germany
Up to now, failure analysis focuses on electronic components. Few publications proceed to-wards subsystems like PCBs, MCMs and new package-related subsystems. But the major challenge of the future will be dedicated to system- and root-cause-oriented failure investiga-tion, where component analysis is one of the analysis entries but not the home stretch to-wards root cause finding. Device analysis needs a careful anamnesis throughout the full supply chain and application, taking into account application-specific issues like duty times, environmental conditions, circuitry, (crosstalk-) pulse/ ESD/ EMV loads and device-to-system-assembly manufacturing aspects. Due to the numerous interfaces, this approach sometimes needs also convincing of the vendors and customers involved. Some illustrative case studies from industry- and automotive electronics show this major failure analysis trend-change in a demonstrative and comprehensive manner; microelectronic components had failed and an “isolated” electrical and physical analysis never would have highlighted the sys-tem-related root causes. The presentation concludes in a checklist of important questions, which should be carefully discussed before starting the electrical and physical failure analysis from device manufacturer’s - as well as from application/ customer’s-point-of-view.
Do we understand the degradation mechanisms of InGaN laser diode?
by TopGaN, Warsaw Area, Poland
In contrast to conventional GaAs based laser diodes, InGaN devices undergone the steady degradation during whole time of their operation. This degradation follows usually quite closely a square-root on time law suggesting the involvement of the diffusion processes. In order to pin-point the diffusing element we performed the detailed study of chemical profiles measured by SIMS in the heavily degraded devices. No Mg not H or Si seem to contribute to the observed process. That may mean the involvement of other more exotic impurities (doubtful), migration of native defect or ordering of known impurities like Mg which does not shift the mass center of their distribution. The degraded devices seem not to be discernible from the point of view of cathodoluminescence contrast which makes a researcher cautious about the simple explanation by the increase of the nonradiative recombination in the active area of the laser diode (quantum wells). No signs of the extended defect propagation or multiplication makes the relation between dislocation density and the lifetime even more puzzling. Finally I would like to discuss the analysis of light-current characteristics in the aged laser diodes which takes into account the droop and stimulated emission.
Reliability issues of GaN based high voltage power devices
by Ferdinand-Braun-Institut, Leibniz Institut für Höchstfrequenztechnik, Germany
GaN based power devices for high efficiency switching applications in modern power electronics are rapidly moving into the focus of world wide research and development activities. Due to their unique material properties GaN power devices are distinguished by featuring high breakdown voltages, low on-state resistances and fast switching properties at the same time. Finally, these properties are the consequences of extremely high field and current densities that are possible per unit device volume or area. Therefore, in order to obtain very high performance, the material itself is stressed significantly during standard device operation and any imperfection may lead to wear out and reliability problems. Thus material quality, the specific epitaxial design as well as the device topology will directly influence device performance, reliability and mode of degradation. The paper will mainly discuss those degradation mechanisms that are especially due to the specific material combinations used in GaN based high voltage device technology such as epitaxial layer design, chip metallizations, passivation schemes and general device topology and layout. It will then discuss technological ways towards engineering reliability into these devices. Generally, device designs are required that effectively minimize high field regions in the internal device or shift them towards less critical locations. Furthermore, an optimized thermal design in combination with suitable chip mounting technologies is required to enable maximum device performance.
Dielectric charging phenomenon in electrostatically driven MEMS/NEMS devices: Nanoscale and macroscale characterization using novel assessment methodologies
by MINC, LAAS, France
Dielectric charging constitutes a major failure mechanism which inhibits the commercialization of various electrostatically actuated micro- and nano-electromechanical systems (MEMS and NEMS). The paper will present numerous novel characterization techniques for this phenomenon based on Kelvin probe force microscopy (KPFM) and adhesive force measurements, in view of application in electrostatic capacitive RF-MEMS switches. The proposed methodologies are performed on the nanoscale and makes use of the atomic force microscope (AFM) tip to simulate a single asperity contact between the switch suspended electrode and the dielectric surface. The discharge current transients (DCT) and thermally stimulated depolarization current (TSDC) assessment methods have also been used to study the charging/discharging processes in (metal-insulator-metal) MIM capacitors. A comparison between the investigated characterization techniques and a correlation between the obtained nanoscale/macroscale results and the literature reported data on MEMS switches will be presented. The influence of the dielectric film thickness, deposition conditions, substrate material, and relative humidity will be discussed. Finally, different stiction mechanisms induced by dielectric charging and/or meniscus formation in electrostatic MEMS switches and characterized by measuring the adhesive and friction forces under different operating conditions will be analyzed.
Accelerated Testing under Complex Loading Conditions: Benefits and Challenges
by IZM Berlin, Germany
will be organized by Richard Langford (University of Cambridge - UK) on Monday October 3rd.
For further information, please visit: www.imec.be/efug/.
will be organized by Mauro Savoia (STMicroelectronics - Italy) on Wednesday October 5th.
This edition will focus on Failure analysis mechanisms in Analog, Power and RF devices and applications.
More info on EUFANET at www.eufanet.org.
will be organized by Eckard WOLFGANG (Germany)
This edition will focus on Reliability of renewable energy systems.
Today's telecommunication satellites as well as the rapid growth of the Internet traffic and the forthcoming broadband services are strongly demanding enabling optical technologies and techniques. For avionics, medical, military, and even telecommunications applications, photonics and solid-state electronics industry faces relentless pressure to improve performance, increase functionality, decrease costs, and reduce design and development time. As a result, packaging solutions carried up, characterization test methods developed, screening and qualification test programs implemented must be driven by physics-of-failure approach to micro-optoelectronics reliability modeling and assessment. Sophisticated failure analysis methodologies require multiple expertise domains: optics, electronics, micro-mechanical systems, thermal, radiation, EMC...
To understand this new coming age for Hi-Rel telecommunications market in aerospace and satellites applications, ISROS committee (International Symposium on Reliability of Optoelectronics for Space) is proposing a half day workshop in conjunction with the ESREF 2011 event dedicated to Packaging and Failure Analysis Techniques of Optoelectronic Devices for Aeronautic and Space Applications.
The workshop will be organized in several discussions with interactive talks on selected topics. Each panel member will be invited to share its experience and advice in the field selected. A final panel discussion will conclude the workshop.
MATERIALS, COMPONENTS MANUFACTURING AND PACKAGING ASSEMBLY TECHNIQUES: